In an ASIC/FPGA (Application Specific Integrated Circuit/Field Programmable Gate Array) utilized in a networking application, a context RAM may be needed to hold the per-port configuration that is specific to that port only. Usually, there are several functional blocks inside the ASIC/FPGA that want to access the context RAM to inquire the configuration of a particular port.
Ideally, only one context RAM is needed. However, if there is more than one functional block that needs access to the context RAM in the same cycle, there needs to be an arbitration scheme to resolve the conflict in a timely manner which would satisfy the required access time of each functional block. If there are more than two such functional blocks, then the design of an arbitration logic is much more complex. To simplify the design, an ideal solution is to duplicate the context RAM such that each functional block accesses its own identical copy of the context RAM.
However, other issues come up while maintaining several identical copies of a context RAM:                1. Each copy of the RAM must be separately updated so that the same information will be instant to all functional blocks that access the RAM.        2. The status of each copy of the RAM must be inquired in a time efficient manner.        3. Each copy of the RAM must be tested with minimum time and least cost, etc.        4. Each copy of the RAM will require a distinct set of addresses; the more copies that are used, the greater the address range needed.        
Accordingly, an improved technique for providing context information to multiple functional units is required.